Executive Outlook: Driving Productivity, CoO in 2008

Franklin Kalk, CTO, Toppan Photomasks Inc.

Like a Silicon Valley day, the 2008 economic landscape will be cloudy early and clear later. It's difficult to predict where the U.S. economy is headed, but the sub-prime mortgage crisis, rising oil prices and a weaker dollar have prompted some economists to utter the "R" word in their forecasts. In turn, the forecast for chip demand is cloudy.

What's easier to predict is the continued downward pressure on average selling prices (ASPs) because of the proliferation of consumer products and increasing memory capacity. Most prognosticators appear to be betting that the net impact of all these factors will be moderate rather than negative, and that the industry will experience high single-digit revenue growth — contingent on clearing skies in the second half of the year.

On the technical side, the "incredible shrinking half-pitch" trend shows no such signs of moderation. This year will be a watershed year for immersion lithography as it achieves volume manufacturing. This, in turn, will place strong demands on mask critical dimension (CD) and topographic accuracy. The sea of flash memory in which we swim will continue on its course toward double patterning (or spacer), placing greater demands on photomask-writer and metrology accuracy.

Extreme ultraviolet (EUV) mask availability is actually an economic question. In fact, EUV's successful implementation in 2013 hinges on the availability in 2008 of a reliable, powerful photon source and robust resist platform. This year could indeed clarify whether EUV will sink or swim.

Tom St. Dennis, Senior Vice President and General Manager, Silicon Systems Group, Applied Materials Inc.

Memory technologies will continue to drive the industry in 2008. Memory makers are seeking the competitive advantages from being first-to-market with next-generation devices, which fuels demand for the next-generation equipment required to scale to advanced nodes. They also benefit from the strong consumer pull for memory-intensive devices such as MP3 players and, ultimately, solid-state disk drives and servers.

The device scaling necessary to enable next-generation NAND flash and DRAM requires overcoming complex challenges, such as the limitations of conventional optical lithography. This drives the adoption of innovative techniques like self-aligned double patterning, which introduces new steps in etch, chemical vapor deposition (CVD), metrology and inspection. As DRAM makers squeeze more bits on each chip, they are introducing new materials to scale the periphery, gates and interconnect. Traditional "logic" technologies, such as oxynitride gate dielectrics, selective silicon epitaxy and copper interconnects, are being reengineered for memory.

In logic, we are seeing a different phenomenon. The makers of consumer-driven logic applications are satisfying demand with existing technologies and ramping greater volume at 65 nm and above. However, the high-end microprocessor makers continue to aggressively scale along Moore's Law's track, scaling to 45 nm and beyond with materials like high-k and metal gate to drive faster devices with significantly less energy consumption.

Solving these and other complex technology challenges in an economically feasible way requires greater collaboration across the industry than ever before. Equipment suppliers must focus on process integration and engage across the industry, working closer with device makers and industry consortia to compress the R&D cycle and bring new products to market quickly.

At the same time, the pressure to increase productivity and reduce cost will be more intense than ever. Across the industry, every aspect of the manufacturing cycle is being scrutinized to maximize efficiency and eliminate waste: Process tool integration, manufacturing execution, asset utilization, energy reduction, dynamic work-flow scheduling and other critical functions are under the microscope.

Through cost-effective, sustainable technologies, we can simultaneously boost fab performance and reduce our environmental impact. By shortening cycle times, lowering water and energy use, recycling silicon and hardware, cutting fab emissions, and increasing the use of clean energy, we can improve productivity, reduce costs and decrease our industry's carbon footprint.

Mike Fister, President and CEO, Cadence Design Systems Inc.

The wide appeal of emerging consumer technology continues to drive the electronics industry to smaller, faster and lower-power devices that must be manufactured quickly in high volumes. In the drive to meet these demanding market requirements, end-product producers must increase functionality, performance and battery life and reduce unit cost. The single point of intersection where all of these factors are influenced is at chip and system design.

The electronic design automation (EDA) industry provides designers with the tools and methodologies needed to deliver on the multitude of end market product requirements, but, going forward, EDA needs to do more — more to enhance core design capabilities and more to bring manufacturing awareness and constraint solutions into the design flow so that they are minimized during manufacturing. In the future, solutions will automatically prevent manufacturing problems and analyze, correct and optimize designs for the best electrical performance, power consumption and manufacturing yield. What does that mean exactly? Well, EDA solutions will automate and preserve low-power design intent; synthesize and debug complex, multi-million-gate mixed-signal chips; and model and correct thousands of nanoscale manufacturing-induced effects faster, earlier and cheaper than ever before. Going forward, we will see techniques emerge for linking embedded software applications with the low-power features of the host chip — the dawn of true electronic system-level (ESL) design software.

Tim Bowe, CEO, Foliage

Increasing productivity of 300 mm fabs continues to be a major focus for the industry through 2008 and beyond. The ISMI 300 mm Prime initiative focuses on the following areas for improving fab productivity:

• Reducing first-wafer delay and setup
• Single wafer/mini-batch furnace process tools
• Improving tool availability

However, the aforementioned apply primarily to new fabs or expansions, but not readily to retrofits in existing fabs — where the need is for 2008. First-wafer delay and setup certainly apply to changing product mixes in existing fabs, but the big driver is getting immediate production out of a new fab. Smaller batch sizes decrease cycle times, but there are significant challenges in changing operational automation systems and logistics for existing fabs. Increasing tool availability in existing factories is also problematic because process tools are already installed and running; upgrading hardware on these tools to increase uptime is difficult and risky.

We believe that the biggest factor in increasing 300 mm fab productivity will be improved tool availability resulting from enhanced software capabilities. Specifically, these include increased effectiveness of identification and diagnosis of problems, increased allowances for remote tool access for problem resolution, improved tool maintenance support systems, and better tool control system reliability and error recovery capabilities.

Walden C. Rhines, CEO, Mentor Graphics

A major wave of change is underway, increasingly commoditizing the digital CMOS logic portion of the semiconductor industry. Although semiconductor foundry alliances are intended to spread the cost of next-generation fabs among multiple organizations, they are having the unintended side effect of reducing the diversity of manufacturing processes. All of this seems to suggest that the semiconductor industry is going fabless, or at least "fab-lite," making design the primary differentiator for both fabless and IDM semiconductor companies alike.

At each step in the design process, advanced technologies are emerging to promote design differentiation. At the system architectural level, designers can now quickly explore trade-offs between performance, area and low power to determine the optimal balance for the target application. That, coupled with the adoption of advanced verification techniques within an integrated verification environment, such as algorithmic test bench synthesis, coverage-driven verification and assertions, greatly improve design implementation accuracy and speed.

On the physical design level, the explosive growth in complexity at 65 nm and below is being addressed by new place-and-route techniques that support multi-corner, multi-mode analysis. And physical yield analysis is creating a powerful feedback loop that connects design with statistical layout analysis to help maximize yields.

Those design companies that take advantage of these techniques to differentiate their digital designs will most assuredly thrive, even in the face of consolidation and commoditization in digital CMOS manufacturing.

Gideon Argov, President and CEO, Entegris

In 2008, we expect to see the impact of the significant additions to industry capacity made over the past two years. Bringing this new capacity up to maximum yield and efficiency in as short amount of time as possible will remain the paramount issue in the industry. Achieving "yield ramp" with the development and deployment of 45 and 32 nm technologies will require an even greater degree of contamination control through the entire manufacturing process. Contamination control has moved beyond the particle level down to the molecular level, and must contend with such defect-causing contamination as airborne molecular contamination (AMC), which is extremely subtle and complicated to identify and control.

Reticle haze is just one example. The cost of defects caused by haze forming on the reticle can be exorbitant and an acute problem in fabs that are deploying next-generation 193 nm wavelength lithography processes. While previous efforts to control reticle haze have achieved only marginal improvements, advancements in key technologies are being made. We expect 2008 to be a breakthrough year for new solutions.

Frank Wicks, President, SAFC

Next year promises to be interesting for the semiconductor industry from a materials and chemistry perspective. With Intel and IBM announcing their intentions to use hafnium-based precursors in their next-generation products, we expect other manufacturers to follow suit. The semiconductor industry, in all of its manifestations, both silicon and III-V, continues to accelerate to meet more technologically challenging design demands. This, in turn, is putting pressure on the supply sectors — photolithography suppliers, wafer suppliers, CMP producers, tool manufacturers, chemicals suppliers and others.

We are witnessing acceleration in the demand for new precursors to operate in an environment that demands shorter times to high-volume manufacturing (HVM). Furthermore, it is likely that such HVM chemicals will have a shorter life cycle, as we anticipate "next-generation" chemicals that will overtake them. This scenario applies across the entire manufacturing sector — be it in logic, memory or other iterations. To effectively manage these situations, there is a requirement for the supply chain to maintain close links and collaboration with overlapping and potentially helpful technologies, particularly as chemical needs become more and more demanding.

Jeroen Bloemhard, Global Executive Director, Electronics and Advanced Technologies Industry, Dow Corning Corp.

We continue to see the number of new materials needed for advanced CMOS grow exponentially with every new DRAM half-pitch technology node (often referred to as "More Moore"). Moreover, we are seeing additional new material requirements arise for complementary devices, such as MEMS and passives ("More Than Moore"). The very nature of the International Technology Roadmap for Semiconductors (ITRS) fosters opportunities for new processes and material applications in low- and high-k dielectrics, high-aspect-ratio gap-fill dielectrics, and dielectrics that can be deposited at lower thermal processing temperatures — particularly for silicon-based photoresists and antireflective coatings because of their superior etch resistance.

In the "More Than Moore" scenario, we see material opportunities evolving with the integration of heterogeneous devices on a single chip (system-on-a-chip [SOC]), as well as from new advanced system-in-a-package (SiP) technologies, such as 3-D integration and wafer-level packaging (WLP) techniques. As predicted, the cost for R&D has been, and will continue to, grow exponentially, highlighting the critical need for collaboration. We continue to see that strategic partnerships between device manufacturers, equipment suppliers and state-of-the-art microelectronics R&D centers will be the most effective way to bring innovative solutions to the market quicker and at a lower cost.

Linda Rae, Executive Vice President and COO, Keithley Instruments Inc.

As advances in traditional CMOS scaling techniques reach their limit, new materials and novel device designs are needed. However, fewer companies can afford the cost by themselves and are relying on R&D partnerships or their foundry suppliers. This approach requires more testing to prove out new technologies not developed in-house. New materials and smaller device structures require new test approaches, such as pulse I-V testing, to minimize thermal effects caused by device stimulation. In addition, new failure mechanisms mean a need for more reliability testing, testing a greater volume of devices, and increasing the need for more test automation in labs.

Accurate modeling of parametric variations is also crucial for gaining a more realistic assessment of circuit and, ultimately, device performance. Consequently, another trend we're seeing is the need for a lot more data at the 65 nm node and below, as parametric variation is having a key impact on fab yield. This puts continued downward pressure on the cost of test as companies require anywhere from 3 to 100 times the amount of data to establish a robust process during process development.

The continued drive for higher bandwidth and high data rate devices is also steering growth in RF chipset technology. As new standards evolve, RF chips will exponentially increase in complexity. Furthermore, greater integration of both chips and packages, such as system-on-a-chip (SOC) packages, will require RF functional test at the wafer level, where the performance of a component such as a power amplifier wafer must be verified before it can be placed in the SOC package. Wafer testing will often require both RF and DC measurements on all points of a test system.

Ludo Deferm, Executive Vice President and Head of Business Development, IMEC

In the field of process technology, there are two main technological challenges for 2008: The development of double-patterning techniques for 193 nm immersion lithography because it is the only option to be ready in time for the 32 nm technology node; and further optimization of high-k and metal gates to make the technology transferable from the 45 to the 32 nm technology node. In the area of packaging, R&D in 2008 will focus on 3-D stack technologies and, more specifically, on the link with suitable design methodologies and algorithms. 3-D technologies are important for industry because it allows achieving a small form factor and high density without necessarily using the smallest technology. And finally, the biggest challenge for 2008 in the area of design remains closing the gap between technology and design.

Joint R&D remains important to deal with the rising R&D costs and risks associated with introducing and ramping new technologies. A new trend is the involvement of foundries in R&D. This is because many companies tend to evolve from a fab-rich to a fab-light model, in which the foundries do the more aggressive technologies. For this reason, foundries and equipment and material suppliers have a stronger need for cost-effective R&D support than ever before. The IDMs will still benefit from joint research, but mainly to acquire basic insight in the latest technologies, with a stronger focus toward design issues.

Jeffrey Spiegelman, Founder and President, RASIRC

With every regional fire, flood, drought or hurricane, it becomes clearer on a personal level that global warming is real. Having just recently been evacuated from my home in San Diego for wild fires that are now a common occurrence in the parched western United States, it is clear to me that technology is the only solution. The rapid growth in both volume and efficiency of photovoltaics will outpace the pundits' predictions of what percent of energy can be derived to move the world from carbon-based to silicon-based. The recent breakthrough of a carbon nanotube radio demonstrates a 25,000× reduction in the size of a radio transmitter, with a related reduction in power requirements. By blending the technology know-how of the semiconductor equipment industry with the rapidly developing R&D processes in alternative energy and nanotechnology, we can effect a change in global warming without returning to the dark ages. We will see very rapid and sustained growth for those companies that develop the equipment, new materials and delivery components needed for these new processes to improve yield and reduce device costs.

Erik Smith, President and COO, Qcept Technologies

Materials innovation will continue to drive much of the performance improvement in semiconductor devices in 2008 and beyond. However, as more materials — and number of process steps associated with their integration — are being added to the manufacturing process, non-visual defects (NVDs) are becoming an increasing concern in the industry. These NVDs include submonolayer metallic and organic residues, charging and other surface non-uniformities. Primarily caused by wafer cleaning — the most repeated process step in the fab — these defects represent as much as 30% of fab defectivity today.

Often, the performance gains enabled by new materials rely on the quality and uniformity of their surface condition. Even trace amounts of residue remaining after cleaning can lead to failure of subsequent processing steps, altered device performance, and long-term reliability degradation. As manufacturers drive yield improvement and cost reduction programs, the ability to detect and mitigate NVDs has become just as important as historical efforts focused on physical defect inspection.

Yet despite their growing significance, detecting NVDs is a challenge. They do not scatter light and are, therefore, invisible to existing optical defect inspection techniques. As cited by the latest International Technology Roadmap for Semiconductors (ITRS): "More circuit failures will be caused by defects that leave no physical remnant. The rapid sourcing of non-visual defects...will become increasingly challenging." This underscores the need for new solutions that can provide fast, inline detection of NVDs to drive yields going forward.

Mihir Parikh, President and COO, Aquest Systems

Increasing productivity of deployed assets in IC fabs will be a significant concern as the industry enters a downturn. The need to improve productivity with no risk to the existing manufacturing capability will be an even bigger concern. Therefore, IC manufacturers will want to carefully evaluate various options and ensure that any implementation for productivity "improvement" will indeed happen — without risk — and will be cost-effective.

Automation, and especially automated material handling systems (AMHS), can either improve or limit productivity. This is especially apparent under manufacturing conditions that require multiple priorities (hot lots or monitor wafers) and disrupt flow and schedules; manufacturing conditions that result in wafer and FOUP congestion caused by equipment downtime or unavailability; or smaller lot sizes, which are needed to enable shorter cycle times and improved equipment utilization. These and other such conditions require the need to have a no-risk productivity improvement strategy and solutions (hardware, software and services) that enable implementation in an operating fab. That is a challenge that the industry and suppliers have to rise to.

David Lazovsky, CEO, Intermolecular

The semiconductor industry presents an intriguing paradox: the extraordinary has become commonplace.

By reliably maintaining Moore's Law and enabling the unprecedented technological and economic benefits stemming from that achievement, the industry has fostered an assumption that the rapid innovation required to continue this historic accomplishment is a given.

Advancements in semiconductor manufacturing technologies, process efficiencies and yield learning improvements have produced critical changes throughout the industry, but the primary goal has always been more efficient production and improved manufacturing ROI.

Today, however, that historical pace of innovation is at risk. The challenges to developing technologies that enable Moore's Law are outstripping our capabilities. Fortunately, we can benefit from the experience of other industries that have radically improved R&D learning rates and R&D ROI by using new approaches. With the application of combinatorial technologies, industries such as biotech, energy, pharmaceuticals and materials have significantly improved R&D efficiency and effectiveness.

Until recently, the primary driver for IC performance was scaling through lithography. Although lithography is still critical, going forward the key driver for IC performance will be innovations in materials and device integration. Building on the industry's unprecedented pace of technology advancement and unlocking the innovation potential embodied within the periodic table will require a new approach to semiconductor R&D.

Joe Cestari, CEO, ILS Technology

Optimizing productivity through predictive maintenance, tool matching, e-manufacturing measures and e-diagnostic initiatives is driving the need for semiconductor manufacturers to evaluate real-time remote connections to equipment suppliers and their maintenance experts. However, many manufacturers have concerns about security and the protection of intellectual property (IP). They want those issues addressed before they establish connectivity and share live data from the equipment in their fabs. It is now imperative that IP protection guidelines and security measures established by industry standards bodies and guideline-setting consortiums are followed closely so that many of these manufacturers get the assurance they need to make remote connectivity technology acceptable.

Through cooperation with organizations such as SEMI, the International Sematech Manufacturing Initiative (ISMI) and other similar region-specific bodies, all of the constituents in the global semiconductor supply chain have been participating in ongoing workshops structured to provide input addressing these manufacturing concerns. All of the input is considered, which has led not only to the set of existing guidelines and standards, but also to continuous review and refinement. These organizations generated the standards that enable live network connections with strict security policies that afford the maximum protection of IP.

Wan Thai Hsu, CTO, Discera

In 2008, we expect to see MEMS continue to evolve, significantly impacting sensing functions, electronic component replacements and 3-D chip integration. This coming year will introduce the concept of implementing multiple MEMS devices on one chip as a MEMS platform to provide various sensing functions to more multi-functional products. With this platform, MEMS will gradually move from "one product, one process" to a more standardized process. We also anticipate that MEMS devices will start replacing existing electronic components that have been used for decades, such as microphones, oscillators, RF switches and displays. Finally, we forecast that MEMS fabrication technologies, which provide a higher aspect ratio than conventional IC processes, will notably enhance 3-D chip integration.

Nigel Hunton, CEO, Edwards

Although the outlook for semiconductor manufacturing equipment is not as strong next year as one might have hoped, we see significant growth opportunities in related markets, such as photovoltaics for solar power generation. Across the board, customers continue to press for reduced cost-of-ownership as they strive to improve their competitive positions. This is increasingly coupled with concerns about the environmental impact of their manufacturing processes. The environmental issues are particularly interesting because they not only present an opportunity for equipment manufacturers to differentiate their products, but are also one of the underlying forces, with the rising cost of conventional energy, which drives growth in the solar energy segment.

Alex Oscilowski, Vice President and COO, Rudolph Technologies Inc.

As an industry, we face significant hurdles in maintaining the pace of development that we have enjoyed since Gordon Moore made his famous observation more than four decades ago. It is interesting to recall that he qualified his statement, applying it only to the number of components per IC "at minimum cost." Few doubt that we can continue to increase the number, performance and capability of electronic devices, but at what cost? Almost universally, our customers seem less concerned about the existence of viable technologies than about their cost; specifically, which will provide the needed capability at the lowest cost?

A number of trends are apparent in our markets in which cost-of-ownership is a primary driver. The industry has moved quickly to embrace automated macro defect inspection, as increases in throughput have lowered its cost. In the automotive sector, chip manufacturers are implementing 100% inspection, putting further emphasis on throughput and cost as they move forward aggressively toward "zero defects." Less obvious, but perhaps even more important, are the cost savings that accrue from the intelligent integration of hardware and software for automatic defect classification, efficient sampling and intelligent review. Finally, as memory manufacturers move to copper interconnects, the technology to measure barrier, seed, electroplate and chemical mechanical planarization (CMP) processes with a single tool is a compelling cost reduction benefit. Cost reduction will undoubtedly play an increasingly important role as our industry moves forward through 2008 and beyond.

Chris Moore, CEO, Advanced Metrology Systems

With market maturity comes specialization, and there is no doubt that the semiconductor industry is maturing. Our customers are specializing in many ways, from the large-volume, low-cost commodity memory providers to highly flexible manufacturing companies, such as the foundries.

In 2008, we expect the trend of maturation and specialization to continue in the semiconductor market as our fab customers strive to differentiate themselves to increase perceived value for their products and improve their own profitability.

This trend in specialization can be clearly seen in the memory business, which has led to various forms of DRAM specifically designed for certain applications -- be it graphics devices or embedded memory, NAND flash for hard disk drive replacement and the ubiquitous iPod and NOR flash. We will see company strategies vary from the desired goal to be first in every category to specialization for a particular market niche and everywhere in between.

We expect 2008 to be a year of turmoil and change for our customers and, of course, for us as we respond to their changing needs. Time to market continues to decrease while the market force rate of change continues to increase. Truly as the saying goes, "May we live in interesting times."

Hans Betz, President and CEO, Advanced Energy Industries Inc.

Across the global semiconductor industry, we continue to see a strong drive for productivity, reliability and sustainability, as well as an emerging need to compensate for the lack of a timely extreme ultraviolet (EUV) solution, which is proving to be a barrier to the economical migration of Moore's Law beyond the 32 nm technology node.

This challenge is being addressed by IC makers through the implementation of double patterning (DP) technology, which will allow them to further shrink the devices and, by some IC makers, through a faster migration to 450 mm wafers.

Both solutions present opportunities and risks to OEMs and their suppliers. DP increases the number and complexity of lithography process steps, requiring significant process control and cost reduction improvements. The 450 mm timelines, on the one hand, level the playing field for competing suppliers and, on the other hand, raise the bar for the independent survivability of supplier companies. Moreover, the 450 mm direction will further encourage strategic collaborations and consolidation in the worldwide supply chain.

The winners in this accelerated wave of cooperation will be those who collaborate with the world's technical leaders in process improvements and advancements, as well as those who invent and deliver enabling technology, which contributes to the advancement of Moore's Law.

Companies who actively collaborate and invent at world-class levels directly enable best-in-class:

• Accuracy and control of critical chamber parameters, such as process power and gas, vapor and liquid flow
• Cost-of-ownership optimization through expert subsystem integration
• Uptime optimization incorporating sophisticated predictive failure techniques

Successful suppliers will be the ones who survive and thrive to win both the 450 mm race as well as the emerging process opportunities derived from sub-32 nm node technology.

André-Jacques Auberton-Hervé, President and CEO, The Soitec Group

While the 2008 economy may be marked by uncertainty, in our industry one thing is sure: green is in. This is pushing designers across the electronics spectrum to look for strategies to help balance power consumption with performance and smaller form factors.

The industry's focus on green design naturally positions silicon on insulator (SOI) as the green substrate. The potential for substantial power savings that SOI offers to chip designers is now supported by more readily available physical intellectual property (IP), offerings by leading foundries, and the concerted efforts of the SOI Industry Consortium.

Looking beyond the traditional high-performance logic markets, we see strength in high-resistivity SOI for cell phones and system-on-a-chip (SOC). Leading chipmakers are positioned to make SOI-based memory — both embedded and dedicated — one of this year's game changers. MEMS integration is another exciting area. Automotive, analog and industrial markets are also looking to SOI for cost savings through monolithic integration and more efficient use of power.

While volume applications in SOI are transitioning to 45 nm on the leading edge, advanced substrate manufacturers are now partnering with chipmakers and labs on substrate development tailored to new design concepts for 32 and 22 nm. The basic research phase for substrates addressing nodes beyond 22 nm, plus new solutions for wider ranges of applications and markets, is now underway. This year will also be marked by an increased focus on fully depleted (FD) SOI for low-power applications. Innovative engineered substrates for III-V applications, especially GaN targeting power-efficient lighting, will make further inroads.

Overall, the coming year will see the advanced substrate industry driven by an ever-diversifying applications base, as governments, industry and consumers make "green" technology an economic imperative.

Eric Meurice, CEO, ASML Holding NV

We expect immersion lithography to be our biggest growth area in 2008. Immersion lithography is now the preferred method for patterning sub-50 nm device layers. NAND memory chipmakers turned to immersion technology last year to manufacture their latest 45 nm chips. This year, DRAM makers will use immersion tools to roll out their next-generation of 55 nm chips. Foundries and logic chipmakers should begin adding immersion systems to their production lines in 2009.

Extreme ultraviolet (EUV) lithography is progressing steadily, while computational lithography, double patterning and other resolution enhancement technologies (RETs) are helping to further extend the capabilities of lithography systems.

John Byers, President, Asymtek

Several technologies will influence package design and, thus, the equipment to assemble the packages. These include package-on-package, corner and edge bonding to stabilize and protect components, and the integration of MEMS devices into high-volume consumer products. The transition from wire bond to flip-chip continues to exhibit strong growth. Memory devices will have the most potential growth in that transition because of the need for increased speed.

Density is increased with the reduced feature size of ICs, leading to higher-density interconnect bumps on larger flip-chip die with smaller bump heights. In these cases, applying flux for reflow challenges dipping and printing methods, driving growth in flux jetting.

The growth of high-power LED packages is another interesting trend. While this departs from traditional logic chip packaging, the LED industry is turning to packaging technologies to solve problems of heat dissipation and high-yield manufacturing. As the value of LED packages increases, production yield becomes more important.

The growth of flip-chip devices adds performance and functionality to electronic packages, but flip-chip is more expensive than wire bonding. As an equipment supplier, the challenge will be to provide solutions that reduce the cost of production and enable greater penetration of these technologies.

Karl H. Funke, President and CEO, Multitest elektronische Systeme GmbH

More functionality in increasingly smaller and more cost-efficient packages is the demand originating from end-user applications behind the main drivers in functional test: cost-of-test reduction and shrinking of package outlines. Chip-scale packages, wafer-level packages, package thicknesses below 0.5 mm and contact pitches down to 0.3 mm will be challenging the test handling technologies as we know them today. Traditional gravity feed and pick-and-place handling will reach physical limits, and even strip test will not be the answer to all future questions.

At the same time, as new technologies need to be developed, the cost of test has to come down with the cost of the devices themselves. Or, looking at it differently, the number of units output per test dollar has to go up. Shorter test times, higher test-site parallelism and significant improvements in overall test efficiency are the logical consequences. For the equipment manufacturers, this means they must provide solutions that can be quickly configured to fast-changing test requirements while, at the same time, guaranteeing high reliability and output. We will see up to 32 test sites in logic test handlers and significantly increasing throughput.

As the uncertainties in the end-user markets ripple through the supply chain, the test floors must also develop faster reaction speeds. Their productions ramps becoming steeper more quickly, creating a formidable challenge for today's equipment and its manufacturers.

Mark Melliar-Smith, CEO, Molecular Imprints Inc.

We believe 2008 will see the emergence of imprint lithography.

The outlook for step and flash imprint lithography (SFIL) adoption in the semiconductor industry is increasingly positive. The insertion point for extreme ultraviolet (EUV) continues to get pushed out and is now beyond 22 nm because of technical challenges that have proved very difficult to solve despite huge R&D investments. Double patterning has emerged as a stop-gap solution for 32 nm, but has significant drawbacks, such as high capital costs, reduction in throughput, CD/overlay issues and increased process steps. Consequently, semiconductor producers stepped up their evaluations of imprint lithography in 2007 and began to publish their results — sub-20 nm features, with 1–2 nm line edge roughness/linewidth roughness and 1 nm CD uniformity have already been produced on test chips.

The infrastructure characteristics of imprint lithography are also driving semiconductor manufacturers to take a serious look at this technology. Imprint leverages the existing optical lithography infrastructure with imprint masks being available from traditional photomask suppliers. In addition, imprint resist and sources are based on familiar i-line technology, helping to make them both affordable and reliable. Further contributing to our positive outlook for imprint lithography adoption is our expectation that new silicon-based non-volatile memory structures will emerge in 2008 that are particularly amenable to imprint lithography.

Imprint lithography is also being used in a variety of other industries, such as patterned media for hard disk drives and photonic crystals on LEDs. These applications are moving into production before the end of the decade, and will provide significant manufacturing experience before the advent of imprint lithography for CMOS.

Gerhard Ruppik, General Manager, Vistec Semiconductor Systems GmbH

Driven by investments in production capacity and technology, 2007 was generally a good year for the industry. However, recent months have shown a clearly slowing market, evidenced by the drop in the industry "book-to-bill" ratio to below 1.0. We expect this trend to continue, as some semiconductor manufacturers have recently announced project postponements and investment reductions.

In the short term, the utilization levels for the foundries will probably not noticeably improve. While the results for 2007 remain positive, the forecasts for 2008 are less beneficial, with a probable 0% growth or even a slight drop below that, announcing a significantly less positive trend.

Despite this news, our sector — process control — has definite opportunities. Investments in technology, optimized with a differentiation strategy, could play a key role in 2008. The most important of these technologies includes immersion lithography, double patterning, the transition from 45 to 32 nm technology and wafer-level packaging.

Gabi Seligsohn, President and CEO, Nova Measuring Instruments Ltd.

The rapid shrink of devices in the semiconductor industry continues to increase the demand on metrology companies to be able to support very critical monitoring schemes. Tolerance for inaccuracies of measurement equipment continues to diminish, and the allowable contribution of measurement instrumentation to the process error budget is now closer than ever to zero. With the consolidation of our industry and the migration of many manufacturers to offshore manufacturing, "copy exactly/intelligently/smartly" has become a key element in ensuring that devices manufactured in different parts of the world yield at the same levels. To allow this to happen, metrology companies are now required to provide fleet matching down to single-angstrom levels between dozens of tools in several locations — doing so in a repeatable fashion. This is the case for standalone metrology tools and more so for integrated metrology tools, where deployment in each fab can amount to dozens of tools in several areas, each connected to a process tool having its own inherent variability.

As long as device shrinks continue, this trend will continue and the specifications will continue to tighten up. Understanding the implications of this phenomenon allows metrology vendors the opportunity to contribute to their customers' economic need for shrink and play a key role in their economic battle for distinction in their respective markets.

J. Tracy Weed, Director, Manufacturing Products Group, Synopsys Inc.

Semiconductor manufacturers are struggling to control costs as they invest in new processes and materials that will extend Moore's Law. While design for manufacturability (DFM) has captured the headlines as an industry panacea, keeping pace with the growing demand for semiconductor content will drive the industry far beyond what DFM alone can provide.

Today, DFM provides a predictive environment that allows designers to accommodate the constraints and variability of a manufacturing process to optimize performance, power, yield and cost. To perform this successfully, a holistic approach must be employed that integrates the analysis and implementation capability of DFM with more rigorous simulation, fab-proven mask synthesis tools and the ability to use real fab data to guide design and manufacturing decisions.

Tomorrow, cost will be even more important in determining the direction of the industry. While technology continues to advance through alliances, there will be increasing pressure to ensure fab assets are utilized efficiently. We will see a growing virtual manufacturing environment in which designs will be "signed off" prior to being placed in the fab. This will ensure the devices will yield at a level consistent with aggressive ROI targets. The EDA industry is ready and uniquely qualified to address these challenges.

Tony Edwards, Vice President and General Manager NanoElectronics Division, FEI Co.

In the coming year, our industry will continue to be driven by economies of scale, where the escalating cost of advanced manufacturing technologies must be more than compensated by improvements in throughput and productivity. For equipment manufacturers, this translates into demand for improved precision and process capability, coupled with pressure to reduce CoO and increase ROI.

The most significant trend in our market for imaging and analysis tools is the rapidly accelerating adoption of S/TEM for process development, process monitoring, yield enhancement and failure analysis. Concurrent developments in automated FIB-based sample preparation have resulted in a fully integrated imaging and analysis solution that can go from wafer to result in an hour. The industry now has a solution that meets the high-resolution requirements for today's advanced processes at a cost that is justified by the value of the information obtained.

Paul Lindner, Vice President and CTO, EV Group

With consumer electronics driving the majority of industry development efforts, the growing commoditization of MEMS and ICs for these applications is creating demand for a significantly lower-cost device module. This necessitates a far less manually oriented manufacturing model.

For equipment makers, this landscape poses challenges that center on time and cost. Thanks to consumers' ever-evolving demands, new products have to come to market so quickly that we have to react in about two-thirds less time. Moreover, although the chips for a cell phone camera may be nowhere near as costly as a laptop IC core, equipment makers' R&D and overhead costs remain high. The industry needs to focus on technology convergence, a key trend that will continue to escalate with the burgeoning consumer electronics market. Taking mature technology that's already being used on the MEMS side and leveraging that development work in the IC market will allow companies to proliferate it with only a few tweaks, leading to significant time and cost savings.

Dwain Aidala, President and COO, sp3 Diamond Technologies

It seems like only yesterday we were talking about the millennium and how all of our computer systems were going to be on the wrong time. Last year I talked about the impact of consumer products as technology drivers, and we definitely have seen that happen during 2007. In fact, we are seeing leading-edge technologies becoming commodities at an accelerating pace. Our lives keep whizzing by with new features and lower prices. That presents a business challenge, but also a great opportunity.

What we have seen over the past year is the trend of advanced technology that greatly increases the efficiency and light output of laser diodes and LEDs for top-of-the-line high-definition TVs that are moving down the application pyramid into higher-volume products that can make use of similar performance improvements. That means that price pressures increase, but so do the business opportunities as the volume increases faster than the price decline. It also means that manufacturers must continue to innovate to stay profitable.

Adrian Kiermasz, President and CEO, Metryx

We see 2008 being another growth year for mass metrology, entering the year with a strong backlog. The 300 mm process control metrology market continues to invest in cost-effective, non-destructive metrology for "on-product" wafer measurement. The trend continues toward increased frequency in metrology measurement checks, especially for advanced technology nodes where new materials and complex process sequences are being introduced.

Improving productivity and decreasing the time to market for new devices are still dominating factors. We have found that device manufacturers continue to invest in technologies that they see as a cost-effective benefit to manufacturing next-generation devices. In particular, 45 and 32 nm nodes suffer a variety of metrology and productivity challenges that need production-ready solutions. Mass metrology is being evaluated and adopted for future use at these nodes, with a number of customers who require measurement capability for critical manufacturing weaknesses.

Jim Mello, Vice President of Business Development, Entrepix

As top-tier OEMs focus their efforts and resources to address the changing market space and keep up with technology to outpace Moore's Law, golden opportunities are being left behind. The business model of acquiring technology to address the entire market space is fading, and OEMs are turning to partnerships with outsource suppliers to address this growing legacy equipment market. This shift brings new opportunities to those companies that can bring resources and knowledge in an efficient and cost-effective way to the customer base.

Outsourcing knowledge and capabilities through partnerships will represent a business model that can thrive. Long-term partnerships are already growing between large OEMs and proven third parties to ensure that much needed end-customer support is addressed. These agreements enable a technical capability that results in equipment and process improvements.

Technology is making the world a smaller place, and more companies are coming together to share information and expertise. Maturing fabs, universities, R&D firms, consortia and complimentary nanotech industries can exploit this opportunity to achieve both innovation and time to market at a more rapid pace.